1. Field of the Invention
The present invention relates to a polishing technology employed in the manufacture of a semiconductor device, particularly, to a polishing pad used for a chemical-mechanical polishing (CMP) as well as to a polishing apparatus and a polishing method using the particular polishing pad.
2. Description of the Related Art
In recent years, vigorous research has been made in an attempt to develop various fine processing technologies to meet tendencies toward a higher degree of integration and higher performance of LSI. The CMP technology is one of the objects of research being made to meet the severe requirement for miniaturization, and is absolutely required in the process of a multi-wiring formation including the steps of flattening the interlayer insulating film, forming a metal plug, and forming a buried wiring layer, and in the process of separating the buried elements.
One of the most serious problems inherent in the CMP process is nonuniformity of the polishing rate over the entire surface of an object to be polished, e.g., a semiconductor wafer. To be more specific, a nonuniform pressure distribution over the entire surface of a wafer causes a nonuniform polishing rate of the wafer, with the result that some surface region of the wafer is polished excessively while the polishing in another surface region is made insufficient. The nonuniformity of polishing is a serious problem which adversely affects seriously the yield and reliability of semiconductor elements, when it comes to, particularly, a large wafer having a diameter of, for example, 8 inches. It should be noted that, in order to employ the CMP technology in the manufacturing process of a semiconductor device in the generation of 0.25 .mu.m such as 256 DRAM, it is necessary to control the film thickness on the order of 0.01 .mu.m, making it very important to develop technology which permits further improving the uniformity of polishing rate over the entire surface of the wafer.
FIG. 1 attached hereto is intended to show what the polishing nonuniformity is in the case where CMP is employed in the step of flattening an interlayer insulating film. As shown in FIG. 1A, a lower wiring layer 211 is formed in a thickness of 0.4 .mu.m or less on a wafer, followed by depositing an interlayer insulating film 212 in a thickness of 1 .mu.m to cover the lower wiring layer 211. What should be noted is that the presence of the lower wiring layer 211 causes the interlayer insulating film 212 to have stepped portions. In the next step, the projecting portions of the interlayer insulating film 212 are removed by CMP to flatten the film 212 as shown in FIG. 1B. Then, contact holes are selectively formed in the film 212 to expose the upper surfaces of the lower wiring layer 211, followed by forming an upper wiring layer 214 connected to the lower wiring layer 211 via contacts 213, as shown in FIG. 1C.
Suppose the chemical-mechanical polishing (CMP) is performed in the process described above with an average polishing amount of 0.5 .mu.m and a uniformity in the polishing rate of .+-.10% over the entire surface of the wafer. In this case, the thickness of the interlayer insulating film 212 above the lower wiring layer 211, which was 1 .mu.m before the CMP step, is rendered nonuniform within a range of between 0.45 .mu.m and 0.55 .mu.m (.DELTA.0.1 .mu.m) after the step of CMP.
The nonuniformity in the thickness of the interlayer insulating film after the CMP step leads directly to a nonuniformity in the over-etching time in RIE in the step of forming contact holes and to a nonuniformity in the resistance values of the contacts, which is derived from a nonuniformity in the diameters of the contact holes. It follows that the nonuniformity in the thickness of the interlayer insulating film after the CMP step leads to a low yield in the manufacture of the semiconductor element. On the other hand, where the CMP technology is employed in the formation of a buried wiring layer, the nonuniform polishing rate over the entire surface of a wafer leads to nonuniform resistance values of the wiring and, thus, to a low yield in the manufacture of the semiconductor device. Such being the situation, it is of high importance to improve the uniformity of the polishing rate in order to employ the CMP technology in the VLSI process.
Various polishing pads are being proposed in an attempt to improve the uniformity of the polishing rate over the entire surface of a wafer. For example, it is proposed in each of Japanese Patent Disclosure (Kokai) No. 58-45861 and Japanese Patent Disclosure No. 57-23965 that a relatively hard polishing pad is mounted on a soft elastic material so as to ensure a local flatness (or suppress dishing) and to improve the polishing uniformity over the entire surface of the wafer. In the technique disclosed in these prior art publications, however, a nonuniform pressure distribution is generated because of the mechanical properties of the soft elastic material itself such as the rigidity (or elasticity) in the horizontal or vertical direction, making it difficult to improve satisfactorily the polishing uniformity over the entire surface of the wafer. In conclusion, the conventional CMP technology fails to suppress sufficiently the nonuniformity in the polishing rate over the entire surface of a wafer, leading to a low yield and impaired reliability of the semiconductor element.
On the other hand, a polishing pad using a fluid cushion in place of the Soft elastic material is proposed in, for example, Japanese Patent Disclosure No. 5-285825 and Japanese Patent Disclosure No. 5-505769 in an attempt to further improve the polishing uniformity of the wafer. In the fluid cushion, the load distribution on the work surface is made uniform on the basis of Pascal's law so as to improve the polishing uniformity. However, the polishing pad using a fluid cushion leaves room for further improvements, as pointed out below with reference to FIG. 2.
Specifically, a fluid cushion 224 prepared by, for example, sealing a gas in a polyethylene bag is arranged between a polishing pad 223 and a polishing base body 225 in the conventional polishing apparatus, as shown in FIG. 2A. In polishing a wafer surface by using the conventional apparatus, each of a polishing head 221 supporting, for example, a semiconductor wafer 222 and the polishing base body 225 of the polishing apparatus is rotated each at 100 rpm. During the rotation, the wafer 222 is pressed against the polishing pad 223 with a load of 300 g/cm.sup.2 while a polishing agent is supplied to the polishing pad 223 through a pipe 227. In the conventional polishing apparatus, however, the polishing pad 223 and the fluid cushion 224 are markedly deformed during the polishing operation, as shown in FIG. 2B. The deformation causes the polishing head to be vibrated. Also, the rotating speed of the polishing head or the polishing pad is rendered unstable. As a result, the uniformity in the polishing rate over the entire surface of the wafer fails to be improved. Also, the stability of the polishing rate tends to be lowered.